This invention relates to a multilayered wiring board carrying a semiconductor device chip and a method for manufacturing the same.
Many of today's microprocessors and memory devices are provided with a multilayered wiring board on which semiconductor device chips and the like are mounted in order to achieve high-density packaging,
Such a multilayered wiring board comprises a board of Si, Al.sub.2 O.sub.3 or AlN, and insulating layers made of SiO.sub.2 or polyimide and wiring layers of Al or Cu, which are alternately laminated on one another, The wiring layers have predetermined wiring patterns formed by combining photolithography, etching and plating. If it is necessary to connect the wiring layers together, they are connected together through via formed in the insulating layers interposed between the adjacent wiring layers.
The wiring layers may have mesh patterns with numerous holes formed therein, Such mesh wiring layers are disclosed in Japanese Unexamined Patent Publications 2-231749 and 3-158002. Such mesh patterns are used to adjust the distributed constant between these layers and the adjacent other layers.
Besides the requirement for high-density packaging, recent microprocessors and memory devices, which operate at an increasingly high speed, are faced with the problem crosstalk produced on the wiring layers of the multilayered wiring board. Namely, the higher the wiring density of the wiring layers and the higher the processing speed, the larger the crosstalk tend to be. Such crosstalk can cause a malfunction of the semiconductor device chip mounted on the multilayered wiring board.
By providing a mesh wiring layer, it becomes possible to adjust the distributed constant between mesh wiring layer and the layers adjacent thereto. However it was impossible to suppress crosstalk between the wirings in one wiring layer.